Frequency synthesizers are key building blocks of wireless communication devices. Before installing, they need to satisfy demanding requirements. Until now, analog PLL synthesizers have been the standard. Now, engineers are focusing on so-called digital PLLs (DPLLs) to achieve ultra-low power operation.
Scientists at Tokyo Tech have devised an advanced phase-locked loop (PLL)1 frequency synthesizer that can potentially reduce power consumption of only 265 microwatts(μW), a figure that is less than half the lowest power consumption achieved to date (980 μW). As scientists noted, this digital PLL could be an attractive building block for Bluetooth Low Energy (BLE) and other wireless technologies to support a wide range of Internet of Things (IoT) applications.
Kenichi Okada, associate professor at Tokyo Tech‘s Department of Electrical and Electronic Engineering said, “The researchers found that overall power consumption could be greatly reduced by using an automatic feedback control system. This automatic-switching feedback path consumes a power of 68 μW, which leads to the power consumption of 265 μW for the whole DPLL.”
The potential applications of the digital PLL include components for processors, memories and a vast new range of IoT devices.
This paper is partially based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO).
This work is being presented in the Frequency Synthesizers session at the 2019 International Solid-State Circuits Conferenceouter (ISSCC), the world’s leading annual forum on solid-state circuits and systems-on-a-chip.