Toshiba developed new bridge chip using PAM 4 to boost SSD speed and capacity

A bridge chip that realizes high-speed and large-capacity SSDs.


In SSDs, numerous flash memory chips are associated with a controller that deals with their operation. As more flash memory chips are connected with a controller interface, operation speed degrades. Thus, there are limits to the number of chips that can be associated.

So as to expand limit, it is important to build the number of interfaces, however, that outcomes in an enormous number of fast signal lines associated with the controller, making it increasingly difficult to implement the wiring on the SSD board.

To overcome this problem, Toshiba Memory Corporation has recently developed a bridge chip that can potentially provide high-speed and large-capacity SSDs. Fabricated by using 28 nm CMOS process, the chip can offer a satisfactory performance of PAM 4 communication by all of the bridge chips and the controller at 25.6 Gbps

This bridge chip connects the controller and flashes memory chips, three novel techniques: a daisy chains connection including the controller and bridge chips in a ring shape; a serial communication using PAM 4 and a jitter improvement technique for eliminating a PLL circuit in the bridge chips.

Toshiba developed new bridge chip using PAM 4 to boost SSD speed and capacity

By using these techniques overhead of the bridge chips are reduced, and it is possible to operate a large number of flash memory chips at high speed with only a few high-speed signal lines.

The bridge chip comes with ring shape configuration and controller reduces the number of transceivers required in the bridge chip from two pairs to one pair. Moreover, developers used PAM 4 serial communication between the controller and the daisy-chained bridge chips that lower the operating speed in the bridge chips’ circuits and relaxes their required performance.

A new CDR that utilizes the characteristics of PAM 4 to improve jitter characteristics eliminates the need for a PLL circuit in the bridge chip, which also contributes to a smaller chip area and lower power consumption. Using this bridge- chip, it is possible to obtain a BER of less than 10-12.

The company is further planning to continue the work toward achieving high-speed, large-capacity storage at levels not yet seen by further enhancing bridge-chip performance while reducing the chip’s area and power consumption.

This result was announced in San Francisco on February 20, at the International Solid-State Circuits Conference 2019 (ISSCC 2019).