To prevent hacker attacks, communication between the chips in the individual components is encrypted. But with time, those encryption techniques become ineffective. Established processes that could fight off attacks introduced with today’s computer technologies would be defenseless against quantum computers. This is especially important for equipment with a long life span, such as industrial facilities.
That’s why security experts from worldwide are working to develop technical standards for ‘post-quantum cryptography. Although, the challenges are presented by the huge preparing power required for these encryption techniques.
Scientists at the Technical University of Munich (TUM) have designed and commissioned a highly efficient chip for post-quantum cryptography. Their innovation could offer protection against future hacker attacks using quantum computers.
What’s exciting is, scientists also incorporated hardware trojans in the chip to analyze methods for detecting this type of ‘malware from the chip factory.’
Their approach is based on hardware/software co-design, in which specialized components and the control software complement one another.
Georg Sigl, Professor of Security in Information Technology at TUM, said, “Ours is the first chip for post-quantum cryptography to be based entirely on a hardware/software co-design approach.”
“As a result, it is around ten times as fast when encrypting with Kyber – one of the most promising candidates for post-quantum cryptography – as compared to chips based entirely on software solutions. It also uses around eight times less energy and is almost as flexible.”
The chip poses post-quantum cryptography capabilities because of a modification of the processor core and special instructions that speed up the necessary arithmetic operations.
Features of the new chip:
- It is an application-specific integrated circuit (ASIC).
- It could implement SIKE 21 times faster than chips using only software-based encryption.
- Incorporates a purpose-designed hardware accelerator.
- Supports lattice-based post-quantum cryptography algorithms such as Kyber.
Hardware trojans evade post-quantum cryptography:
Hardware Trojans are yet another potential threat to chips. If attackers succeed in planting trojan circuitry in the chip design before or during the manufacturing stage, this could have disastrous consequences.
Georg Sigl said, “We still know very little about how real attackers use hardware trojans. To develop protective measures, we need to think like an attacker and develop and conceal our trojans. In our post-quantum chip, we have therefore developed and installed four hardware trojans, each of which works in an entirely different way.”
Soon, scientists will test the chip’s cryptography capabilities and functionality and the detectability of the hardware trojans. They will then destroy the chip for research purposes. In a complex process, the circuit pathways will be shaved off incrementally while photographing each successive layer.
Georg Sigl said, “These reconstructions can help to detect chip components that perform functions unrelated to the chip’s actual tasks and which may have been smuggled into the design. Processes like ours could become the standard for taking random samples in large orders of chips. Combined with effective post-quantum cryptography, this could help us to make hardware more secure – in industrial facilities as well as in cars.”
- Franzmann, T., Sigl, G., & Sepúlveda, J. RISQ-V: Tightly Coupled RISC-V Accelerators for Post-Quantum Cryptography. IACR Transactions on Cryptographic Hardware and Embedded Systems, 2020(4), 239-280. DOI: 10.13154/tches.v2020.i4.239-280
- Roy, D. B. , Fritzmann, T., Sigl G. 2020. Efficient hardware/software co-design for post-quantum crypto algorithm SIKE on ARM and RISC-V based microcontrollers. In Proceedings of the 39th International Conference on Computer-Aided Design (ICCAD’ 20), Article 35, 1–9. DOI: 10.1145/3400302.3415728
- Hepp, A., Sigl G. Tapeout of a RISC-V crypto chip with hardware trojans: a case-study on trojan design and pre-silicon detectability. In Proceedings of the 18th ACM International Conference on Computing Frontiers (CF ’21).213–220. DOI: 10.1145/3457388.3458869