Annealing processors (APs) are gaining popularity for solving complex optimization problems. Fully-coupled Ising model APs are especially valued for their flexibility, but balancing capacity (number of spins) and precision (interaction bit width) remains a challenge due to the complexity of spin couplings.
Previous research has developed systems that scale up the number of spins by spreading calculations across multiple chips, but precision remains limited.
A team from Tokyo University of Science has unveiled a revolutionary dual-scalable annealing processing system (DSAPS) capable of tackling combinatorial optimization problems (COPs) with unprecedented precision and scalability.
Led by Professor Takayuki Kawahara, the study introduces a new approach to annealing processors (APs), which are specialized hardware designed to solve optimization problems in areas like shift scheduling, traffic routing, and drug development.
Traditional computers struggle to solve COPs efficiently, as these problems require evaluating countless possible solutions within a practical timeframe. Based on the Ising model, annealing processors (APs) simplify this process by representing COP variables as magnetic spins, with interactions between them determining the system’s energy state. The optimal solution corresponds to the lowest energy configuration; however, existing models have limitations in terms of scalability and precision.
There are two primary types of Ising models:
- Sparsely-coupled models: Highly scalable, allowing more spins but requiring a transformation of COPs to fit the system.
- Fully-coupled models: More flexible, allowing direct mapping of COPs without transformation, but traditionally constrained by limited capacity and precision.
Previous studies attempted to enhance fully coupled models using application-specific integrated circuits (ASICs). Still, they faced restrictions due to fixed interaction bit widths, limiting their ability to solve specific optimization problems.
In their study, published in IEEE Access (March 21, 2025) and presented at the 2024 International Conference on Microelectronics, Professor Kawahara’s team introduced DSAPS, a system capable of simultaneously scaling capacity and precision without compromising efficiency.
DSAPS relies on ∆E blocks, the computational units responsible for determining the system’s energy. It achieves dual scalability through two key structures:
- High-capacity structure: Divides each ∆E block into smaller sub-blocks, allowing for an increase in the number of spins.
- High-precision structure: Uses multiple ∆E blocks operating at different bit levels, combining them to expand interaction bit-width, improving accuracy.
This novel approach enables DSAPS to increase spin capacity while enhancing precision, a feat previously unattainable in fully coupled models.
To showcase the system’s effectiveness, researchers implemented two DSAPS configurations:
- 2048 spins with 10-bit interactions across four threads.
- 1024 spins with 37-bit interactions across two threads.
These configurations significantly outperformed traditional ASIC implementations, which typically operate with only 4 to 8-bit interactions. DSAPS achieved over 99% accuracy in validation tests for solving MAX-CUT problems, demonstrating its potential for addressing real-world optimization challenges.
However, results varied in 0-1 knapsack problems, where precision was critical. The 10-bit interaction model exhibited a 99 percent deviation, whereas the 37-bit configuration reduced it to 0.73 percent, underscoring the importance of aligning DSAPS configurations with the specific characteristics of the problem being solved.
“This system will prove crucial in developing scalable annealing processors for solving complex real-world problems,” said Professor Kawahara. He also announced plans to integrate DSAPS into semiconductor design education, allowing third-year students to experiment with fully coupled Ising machines starting in 2025.
Journal Reference:
- Dong Cui; Taichi Megumi; Akari Endo; Takayuki Kawahara. Dual Scalable Annealing Processing System That Scales Number of Spins and Interaction Bit Width Simultaneously. IEEE Access. DOI: 10.1109/ACCESS.2025.3553542
